I. Field of the Invention
The invention generally relates to printed wiring boards (PWB's) for use with surface mount integrated circuit (IC) devices such as Field Programmable Gate Array (FPGA) devices and in particular PWBFPGA's employed to emulate Application Specific Integrated Circuits (ASIC's) to the PWB.
II. Description of the Related Art
ASIC's are increasingly employed to perform data processing functions within electronic products, such as cellular telephones, computer devices, and the like. ASIC's are often preferred over non-application specific IC's, such as microprocessors, because ASIC's can be designed to perform sophisticated, specialized data processing at higher processing speeds than can be achieved using, for example, microprocessors. Attaining high processing speeds is often a critical consideration for many electronic products, especially products such as digital cellular telephones wherein a significant amount of data processing must be performed in real-time.
In the present highly competitive marketplace for electronic products, it is particularly important to be able to quickly develop new electronic products to maintain competitiveness. Unfortunately, a considerable amount of time is often requiring to design, fabricate and test the ASIC's to be employed in the electronic product. Moreover, the design of the ASIC is often dependent upon the design of system software which may be developed concurrently with the ASIC. Hence, changes to system software can require corresponding changes to the ASIC. Furthermore, even the basic specifications of the overall system or product may undergo revisions as the ASIC is being developed, thereby typically necessitating changes to the ASIC.
One technique for expediting the development of an ASIC is to employ one or more FPGA's to emulate the ASIC. The design cycle for an FPGA is typically much shorter than that of an ASIC and an FPGA can be easily and quickly reconfigured. Indeed, FPGA's are typically bought "off the shelf" and merely programmed via software to perform selected functions. Hence, the design of the ASIC can be developed, modified and tested relatively quickly using FPGA-emulation before the actual ASIC is fabricated. In particular, FPGA emulation allows for the relatively fast incorporation of modifications required in response to design changes necessitated by software or specification changes, or by correction of bugs and the like. Also the use of FPGA's to emulate an ASIC allows other components of the overall product or system or of a motherboard of the system to be tested as if the ASIC were present. In this regard, one or more FPGA's are connected to a motherboard to functionally replace the ASIC thereby allowing the motherboard or the entire product or system including the motherboard to be tested.
To emulate an ASIC using FPGA's, a PWB is fabricated to provide appropriate interconnection paths for interconnecting input/output pins of the FPGA's to each other or to external input/output devices and power sources. Some of the input/output pins of the FPGA are "fixed" pins dedicated to performing predefined functions such as providing power to the FPGA, programming the FPGA or resetting the operation of the FPGA. Other input/output pins of the FPGA are "user programmable pins" configurable by the user to route input to and output from the FPGA to, for example, facilitate emulation of the ASIC.
The input/output pins of the FPGA are coupled to a set of terminal areas (pads) on the PWB having a "footprint" configured to match the physical arrangement of the pins of the FPGA. FIG. 1 illustrates a conventional footprint 10 having a square arrangement of terminal areas 12 for use as part of a PWB configured to receive an FPGA having a square arrangement of input/output pins. Terminal areas for connection to fixed pins of the FPGA are connected to the appropriate external devices, such as power sources, via internal traces within the PWB. Terminal areas for connection to user programmable pins of the FPGA are typically connected by traces on the top surface of the PWB to plated through hole vias which, in turn, provide interconnection to other traces typically formed within inner layers of the PWB. The other traces typically interconnect with still other vias, which provide interconnection to other surface traces for connection back to the terminal areas of the FPGA or to the terminal areas of other devices on the PWB such as other FPGA's. Often, a fairly complicated network of interconnection paths is provided within the PWB. The PWB with the FPGA's and other devices mounted thereon is referred to as a circuit card assembly (CCA).
FIG. 2 illustrates a portion of a PWB having the footprint of FIG. 1 and also having an exemplary arrangement of vias and surface traces connected thereto. More specifically, FIG. 2 illustrates a set of surface traces 16 connecting a set of vias 18 to the terminal areas 12 of footprint 10. As can be seen, the vias are positioned adjacent to the terminal areas with each terminal area connected to a single respective via by a single surface trace. Although not shown in FIG. 2, additionally traces are provided on inner layers of the PWB which selectively interconnect the vias to one another or to the vias of other footprints for use with other FPGA's to thereby provide appropriate interconnection paths for the FPGA's.
The network of interconnection paths of the PWB for interconnecting the various terminals areas, vias, external pins, powers sources, etc. is typically designed using a computer routing tool which inputs a "netlist" defining how the pins of the FPGA interconnect to external pins or power sources. Typically the routing tool assumes that the footprint for use with the FPGA includes only the aforementioned terminal areas (FIG. 1) and operates to determine the location of all traces and all vias (FIG. 2). The routing tool converts the netlist into a set of specific interconnection paths formed from combinations of terminal areas, surface traces, vias and inner layer traces. The netlists often also include information specifying the required impedance for each path as well as other physical and electrical considerations such as any minimum spacing requirements between adjacent traces or vias. The routing tools are often designed to attempt to provide a set of interconnection paths that maximize performance while also minimizing mass production fabrication costs. Performance is maximized, typically, by providing the most compact possible network of interconnection paths providing the shortest possible signal paths with the lowest impedance. Typically this results in a PWB design having multiple internal layers of interconnection paths employing closely-spaced traces and vias. The traces are often arranged on inner layers of the PWB, rather than on the surface, to control and minimize impedance. Mass production costs are minimized, typically, by arranging the traces to provide a network of interconnection paths that requires the fewest and easiest steps to fabricate.
A PWB is then fabricated using the arrangement of interconnection paths defined by the routing tool and the FPGA's and other devices are mounted to the terminal areas footprints of the PWB to yield CCA. The FPGA's are programmed using the fixed programming pins of the FPGA to emulate the function of the ASIC. The CCA may then be mounted within a system having still other components. The functionality of the CCA or of the entire system is then tested (using any of a variety of conventional techniques), which in turn serves to test the design of the ASIC that the FPGA's are configured to emulate. If design flaws are detected, the FPGA's are redesigned to emulate a modified ASIC design and the process is repeated, i.e., the computer routing tool is employed to define a new set of interconnection paths, based on a new netlist of the redesigned FPGA, and a new PWB is fabricated for use with FPGA's programmed with the new design. This process continues until the design and functionality of the ASIC has been verified, then the ASIC itself is fabricated and tested.
As noted, because the cycle time to program and test an FPGA is much quicker than the cycle time required to design, fabricate and test an ASIC, the overall cycle time to develop an ASIC is expedited by employing FPGA's to emulate and test the ASIC design. Hence, the overall time required to develop a new electronic product employing the ASIC, such as a new cellular telephone or computer device is also expedited.
Although the use of FPGA's to emulate ASIC's has proven to be quite successful, room for improvement remains. One disadvantage relates to the PWB's that contain the interconnection paths employed for use with the FPGA's. Changes to an FPGA often necessitate changes to the interconnection paths. Hence, once any particular FPGA is redesigned, perhaps to remedy a design flaw in the ASIC that it is emulating, the PWB that was fabricated to provide interconnection paths for use with the previous FPGA design typically can no longer be used and is merely discarded. Hence, any CCA's that had been fabricated using the PWB are also discarded. Time and effort is required to fabricate a new PWB providing interconnection paths appropriate for use with the new FPGA design. A new CCA is then fabricated by mounting FPGA's and other devices to the new PWB and the FPGA's are programmed using the new FPGA design. Although the fabrication of a new CCA is much less expensive than that of an ASIC, such fabrication may still be expensive, particularly for CCA's having PWB's providing high density interconnection paths on multiple layers.
In some cases, redesign of the FPGA does not necessitate a new set of interconnection paths. This may occur, for example, if the redesign of the FPGA is purely internal and does not affect the pinout of the FPGA. In those cases, the FPGA mounted is merely reprogrammed by downloading the new configuration of the FPGA while is sits in-circuit within the CCA and then the CCA or the system it forms a part of is tested again. In rare cases, even if new interconnection paths are necessitated, changes to the interconnection paths can be accommodated merely by re-working selected interconnection paths of the CCA, perhaps by severing existing traces that are no longer required and by employing jump wires to provide new required paths between existing vias. If such is the case, the FPGA is merely reprogrammed and the interconnection paths of the CCA are re-worked to accommodate the new FPGA.
Unfortunately, the manner by which interconnection paths are conventionally routed on a PWB of the CCA usually prevents re-working of the interconnection paths merely by manually severing traces and providing jump wires. As noted above, computer routers are typically designed to determine the positions of all vias and traces for use with a fixed terminal footprint to generate compact interconnection path networks which maximize performance and minimize mass production costs. None of these considerations, however, is particularly advantageous when configuring PWB's to be used within CCA's only for testing ASIC-emulating FPGA's. Indeed, these considerations typically yield a network of interconnection paths that is difficult or impossible to re-work by severing traces and providing jump wires. In many cases, traces that need to be severed often lie within inner layers of the PWB and therefore cannot be severed. Even if the trace to be severed is on the surface, the trace may be too short or may be too closely spaced to other traces to be easily manually severed. Also in many cases, vias that need to be connected by jump wires may be buried, semi-buried or blind vias not accessible for reconnection using jump wires. Hence, largely because of the manner by which interconnection paths are conventionally routed and particularly because the router assumes a standard footprint that includes only terminal areas and determines the position of all vias and traces for use with that footprint, even a relatively simple modification to the interconnection path network cannot be accommodated without requiring fabrication of a new CCA incorporating a new PWB. Moreover, even if the network of interconnection paths can, in theory, be manually re-worked, it may be too difficult or time consuming to determine how the network is to be re-worked to make such a reconfiguration worthwhile. Also, if the pitch size of the PWB is too small, it may not be practical to manually reroute the PWB even if otherwise possible. Hence, if manual re-working is to be feasible, it is often necessary to employ a pitch size that is relatively large, which may be otherwise undesirable.
Accordingly it would be desirable to provide a technique for allowing CCA's to be more easily re-used in connection with redesigned FPGA's or other surface mount devices. In particular, it would be desirable to provide an enhanced footprint on the PWB of the CCA that maximizes the chances that a redesigned FPGA can be easily accommodated merely by re-working the interconnection paths of the PWB by, for example, manually severing traces and connecting jump wires. It is also desirable to provide an enhanced footprint that permits re-working even small pitch devices. Aspects to the invention are directed to these ends.